* Voltage : VDD, VDDQ 3.3V All device pins are compatible with LVTTL interface 90Ball FBGA with 0.8mm of pin pitch All inputs and outputs referenced to positive edge of system clock Data mask function by DQM0,1,2 and 3
* Internal four
HY5V52FP Datasheet (357.00 KB)
HY5V52FP
Hynix Semiconductor
357.00 KB
4banks x 2m x 32bits synchronous dram.
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Preliminary HY5V52(L)F(P) Series 4Banks x 2M x 32bits Synchronous DRAM Document Title
4Bank x 2M x 32bits Synchronous DRAM
Revis.
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