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ICS542 Datasheet

Clock Divider

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Description
The ICS542 is a cost effective way to produce a
high quality clock output divided from a clock
input. The chip accepts a clock input up to
156 MHz, and produces a divide by 2, 4, 6, 8, 12,
or 16 of the input clock. There are two outputs on
the chip, one being a low-skew divide by two of
the other. So, for instance, if a 100 MHz clock is
used, the ICS542 can produce low skew 50 MHz
and 25 MHz clocks, or low skew 25 MHz and
12.5 MHz clocks. The chip has an all-chip power
down mode that stops the outputs low, and an OE
pin that tri-states the outputs.
The ICS542 is a member of the ICS
ClockBlocks™ family of clock building blocks.
See the ICS541 and ICS543 for other clock
dividers, and the ICS501, 502, 511, 512 and 525
for clock multipliers.
ICS542
Clock Divider
Features
• Packaged as 8 pin SOIC
• ICS’ lowest cost clock divider
• Low skew (500ps) outputs. One is ÷ 2 of other.
• Easy to use with other generators and buffers
• Input clock frequency up to 156 MHz
• Output clock duty cycle of 45/55
• Power Down turns off chip
• Output Enable
• Advanced, low power CMOS process
• Operating voltages of 3.0 to 5.5 V
Block Diagram
VDD GND
S1, S0
2
Output
Buffer
CLK
Divider and
Selection
Circuitry
÷2
Input Clock
Output
Buffer
CLK/2
OE (both outputs)
MDS 542 B
1
Revision 050400
Printed 11/14/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com




ICST

ICS542 Datasheet Preview

ICS542 Datasheet

Clock Divider

No Preview Available !

ICS542
Clock Divider
Pin Assignment
ICLK
VDD
GND
S0
18
27
36
45
8 pin SOIC
CLK
CLK/2
OE
S1
Clock Decoding Table
S1 S0 CLK CLK/2
0 0 Power Down All
0 1 Input/6 Input/12
1 0 Input/8 Input/16
1 1 Input/2 Input/4
0 = connect directly to ground.
1 = connect directly to VDD.
Pin Descriptions
Number
1
2
3
4
5
6
7
8
Name
ICLK
VDD
GND
S0
S1
OE
CLK/2
CLK
Type
CI
P
P
I
I
I
O
O
Description
Clock input.
Connect to +3.3V or +5V.
Connect to ground.
Select 0 for output clock. Connect to GND or VDD. Internal pull-up.
Select 1 for output clock. Connect to GND or VDD. Internal pull-up.
Output Enable. Tri-states both output clocks when low. Internal pull-up.
Clock output per Table above. Low skew divide by two of pin 8 clock.
Clock output per Table above.
Key: CI = clock input, I = input, O = output, P = power supply connection
External Components
The ICS542 requires a 0.01 µF decoupling capacitor to be connected between VDD and GND. It must
be connected close to the ICS542 to minimize lead inductance. No external power supply filtering is
required for this device. A 33 series terminating resistor can be used next to each output pin. If a 3.3 V
input clock is applied to the ICLK pin, with the ICS542 at 5 V, the clock must be AC coupled.
MDS 542 B
2
Revision 050400
Printed 11/14/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com


Part Number ICS542
Description Clock Divider
Maker ICST
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ICS542 Datasheet PDF





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