ICS541 divider equivalent, preliminary information pll clock divider.
* Packaged in 8 pin SOIC
* Low cost clock divider
* Low skew (500ps) outputs. One is ÷ 2 of other.
* Easy to use with other generators and buffers
* I.
Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary env.
The ICS541 is a cost effective way to produce a high quality clock output divided from a clock input. The chip accepts a clock input up to 135 MHz at 3.3 V, and by using proprietary Phase Locked Loop (PLL) techniques, produces a divide by 1, 2, 4, or.
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