Title | 9DB SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
Description | The ICS9DB102 zero-delay buffer supports PCI Express clocking requirements. The ICS9DB102 is driven by a differential SRC output pair from an ICS CK410/CK505-compliant main clock. It attenuates jitter on the input clock and has a selectable PLL Band Width to maximize performance in systems with or without Spread-Spectrum clocking. Output Features • 2 - 0.7V current mode differential output pairs (... |
Features |
• 2 - 0.7V current mode differential output pairs (HCSL) Features/Benefits • CLKREQ# pin for outputs 1 and 4/output enable for Express Card applications • PLL or bypass mode/PLL can dejitter incoming clock • Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL’s • Spread Spectrum Compatible/tracks spreading input clock for low EMI •... |
Datasheet |
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Distributor |
![]() Quest Components |
Stock | 6 In stock |
Price |
6 units: 3.411 USD 2 units: 4.548 USD 1 units: 6.822 USD
|
BuyNow |
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Distributor | Stock | Price | BuyNow |
---|---|---|---|
![]() Quest Components |
6 units: 3.411 USD 2 units: 4.548 USD 1 units: 6.822 USD |
BuyNow |
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