ICSSSTUAF32866C buffer equivalent, 25-bit configurable registered buffer.
* 25-bit 1:1 or 14-bit 1:2 registered buffer with parity check
functionality
* Supports SSTL_18 JEDEC specification on data inputs
and outputs
* Supports LV.
* DDR2 Memory Modules
* Provides complete DDR DIMM solution with
*
ICS98ULPA877A or IDTCSPUA877A Ideal for D.
This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8-V CMOS drivers.
Image gallery
TAGS
Manufacturer
Related datasheet
Download (Size : 669.33KB)