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ICSSSTUAF32866C Datasheet - IDT

25-BIT CONFIGURABLE REGISTERED BUFFER

ICSSSTUAF32866C Features

* 25-bit 1:1 or 14-bit 1:2 registered buffer with parity check functionality

* Supports SSTL_18 JEDEC specification on data inputs and outputs

* Supports LVCMOS switching levels on C0, C1, and RESET inputs

* Low voltage operation: VDD = 1.7V to 1.9V

* Drop-

ICSSSTUAF32866C General Description

This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8-V CMOS drivers that have been optimized to drive the DDR-II DIMM.

ICSSSTUAF32866C Datasheet (669.33 KB)

Preview of ICSSSTUAF32866C PDF

Datasheet Details

Part number:

ICSSSTUAF32866C

Manufacturer:

IDT

File Size:

669.33 KB

Description:

25-bit configurable registered buffer.
www.DataSheet4U.com DATASHEET 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 ICSSSTUAF32866C design of the ICSSSTUAF32866C must ensure that the out.

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ICSSSTUAF32866C 25-BIT CONFIGURABLE REGISTERED BUFFER IDT

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