ICSSSTUAF32865A Overview
Description
This 28-bit 1:2 registered buffer with parity is designed for 1.7V to 1.9V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18.
| Part | ICSSSTUAF32865A |
|---|---|
| Description | 25-BIT CONFIGURABLE REGISTERED BUFFER |
| Manufacturer | IDT |
| Size | 453.17 KB |
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