Datasheet Details
| Part number | ICSSSTUAF32865A |
|---|---|
| Manufacturer | IDT |
| File Size | 453.17 KB |
| Description | 25-BIT CONFIGURABLE REGISTERED BUFFER |
| Datasheet | ICSSSTUAF32865A_IDT.pdf |
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Overview: .. DATASHEET 28-BIT 1:2 REGISTERED BUFFER WITH PARITY IDT74SSTUBF32865A The IDT74SSTUBF32865A includes a parity checking function. The IDT74SSTUBF32865A accepts a parity bit from the memory controller at its input pin PARIN, pares it with the data received on the D-inputs and indicates whether a parity error has occurred on its open-drain PTYERR pin (active LOW).
| Part number | ICSSSTUAF32865A |
|---|---|
| Manufacturer | IDT |
| File Size | 453.17 KB |
| Description | 25-BIT CONFIGURABLE REGISTERED BUFFER |
| Datasheet | ICSSSTUAF32865A_IDT.pdf |
|
|
|
This 28-bit 1:2 registered buffer with parity is designed for 1.7V to 1.9V VDD operation.
All clock and data inputs are patible with the JEDEC standard for SSTL_18.
The control inputs are LVCMOS.
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