Datasheet Details
| Part number | ICSSSTUAF32866C |
|---|---|
| Manufacturer | IDT |
| File Size | 669.33 KB |
| Description | 25-BIT CONFIGURABLE REGISTERED BUFFER |
| Datasheet | ICSSSTUAF32866C_IDT.pdf |
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Overview: .. DATASHEET 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 ICSSSTUAF32866C design of the ICSSSTUAF32866C must ensure that the outputs will remain low, thus ensuring no glitches on the output. The device monitors both DCS and CSR inputs and will gate the Qn outputs from changing states when both DCS and CSR inputs are high. If either DCS and CSR input is low, the Qn outputs will function normally. The RESET input has priority over the DCS and CSR control and will force the outputs low. If the DCS-control functionality is not desired, then the CSR input can be hardwired to ground, in which case, the setup-time requirement for DCS would be the same as for the other D data inputs. Package options include 96-ball LFBGA (MO-205CC).
| Part number | ICSSSTUAF32866C |
|---|---|
| Manufacturer | IDT |
| File Size | 669.33 KB |
| Description | 25-BIT CONFIGURABLE REGISTERED BUFFER |
| Datasheet | ICSSSTUAF32866C_IDT.pdf |
|
|
|
This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation.
All clock and data inputs are patible with the JEDEC standard for SSTL_18.
The control inputs are LVCMOS.
| Part Number | Description |
|---|---|
| ICSSSTUAF32866B | 25-BIT CONFIGURABLE REGISTERED BUFFER |
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| ICSSSTUAF32868B | 28-BIT CONFIGURABLE REGISTERED BUFFER |
| ICSSSTUAF32869A | 14-BIT CONFIGURABLE REGISTERED BUFFER |
| ICSSSTUAH32865A | 25-BIT CONFIGURABLE REGISTERED BUFFER |
| ICSSSTUAH32868A | 28-BIT CONFIGURABLE REGISTERED BUFFER |
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