Datasheet4U Logo Datasheet4U.com

ICSSSTUAF32869A Datasheet 14-bit Configurable Registered Buffer

Manufacturer: IDT

Overview: .. DATASHEET 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 ICSSSTUAF32869A The ICSSSTUAF32869A includes a parity checking function. The ICSSSTUAF32869A accepts a parity bit from the memory controller at its input pin PARIN one or two cycles after the corresponding data input, pares it with the data received on the D-inputs and indicates on its opendrain PTYERR pin (active low) whether a parity error has occurred. The number of cycles depends on the setting of C1. When used as a single device, the C1 input is tied low. When used in pairs, the C1 inputs is tied low for the first register (front) and the C1 input is tied high for the second register. When used as a single register, the PPO and PTYERR signals are produced two clock cycles after the corresponding data input. When used in pairs, the PTYERR signals of the first register are left floating. The PPO outputs of the first register are cascaded to the PARIN signas on the second register (back). The PPO and PTYERR signals of the second register are produced three clock cycles after the corresponding data input. Parity implimentation and device wiring for single and dual die is described in the diagram below. If an error occurs, and the PTYERR is driven low, it stays low for two clock cycles or until RESET is driven low. The DIMM-dependent signals (DCKE, DCS, CSR and DODT) are not included in the parity check putations. All registers used on an individual DIMM must be of the same configuration, i.e single or dual die.

Datasheet Details

Part number ICSSSTUAF32869A
Manufacturer IDT
File Size 529.65 KB
Description 14-BIT CONFIGURABLE REGISTERED BUFFER
Datasheet ICSSSTUAF32869A_IDT.pdf

General Description

The ICSSSTUAF32869A is 14-bit 1:2 registered buffer with parity, designed for 1.7 V to 1.9 V VDD operation.

All clock and data inputs are patible with the JEDEC standard for SSTL_18.

The control inputs are LVCMOS.

Key Features

  • 14-bit 1:2 registered buffer with parity check functionality.
  • Supports SSTL_18 JEDEC specification on data inputs and outputs.
  • 50% more dynamic driver strength than standard SSTU32864.
  • Supports LVCMOS switching levels on C1 and RESET inputs.
  • Low voltage operation: VDD = 1.7V to 1.9V.
  • Available in 150 BGA package.

More Datasheets from IDT

Part Number Description
ICSSSTUAF32865A 25-BIT CONFIGURABLE REGISTERED BUFFER
ICSSSTUAF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER
ICSSSTUAF32866C 25-BIT CONFIGURABLE REGISTERED BUFFER
ICSSSTUAF32868A 28-BIT CONFIGURABLE REGISTERED BUFFER
ICSSSTUAF32868B 28-BIT CONFIGURABLE REGISTERED BUFFER
ICSSSTUAH32865A 25-BIT CONFIGURABLE REGISTERED BUFFER
ICSSSTUAH32868A 28-BIT CONFIGURABLE REGISTERED BUFFER
ICSSSTVA16859C DDR 13-Bit to 26-Bit Registered Buffer
ICS1523 Video Clock Synthesizer
ICS1526 Video Clock Synthesizer

ICSSSTUAF32869A Distributor