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ICSSSTUAF32868B - 28-BIT CONFIGURABLE REGISTERED BUFFER

General Description

This 28-bit 1:2 configurable registered buffer is designed for 1.7V to 1.9V VDD operation.

All inputs are compatible with the JEDEC standard for SSTL_18, except the chip-select gate-enable (CSGEN), control (C), and reset (RESET) inputs, which are LVCMOS.

Key Features

  • 28-bit 1:2 registered buffer with parity check functionality.
  • Supports SSTL_18 JEDEC specification on data inputs and outputs.

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Datasheet Details

Part number ICSSSTUAF32868B
Manufacturer IDT
File Size 569.86 KB
Description 28-BIT CONFIGURABLE REGISTERED BUFFER
Datasheet download datasheet ICSSSTUAF32868B Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.DataSheet4U.com DATASHEET 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 ICSSSTUAF32868B QERR pin (active low). The convention is even parity, i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit. To calculate parity, all DIMM-independent D-inputs must be tied to a known logic state. If an error occurs and the QERR output is driven low, it stays latched low for a minimum of two clock cycles or until RESET is driven low. If two or more consecutive parity errors occur, the QERR output is driven low and latched low for a clock duration equal to the parity error duration or until RESET is driven low.