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ICSSSTUAF32868A - 28-BIT CONFIGURABLE REGISTERED BUFFER

Description

This 28-bit 1:2 configurable registered buffer is designed for 1.7V to 1.9V VDD operation.

All inputs are compatible with the JEDEC standard for SSTL_18, except the chip-select gate-enable (CSGEN), control (C), and reset (RESET) inputs, which are LVCMOS.

Features

  • 28-bit 1:2 registered buffer with parity check functionality.
  • Supports SSTL_18 JEDEC specification on data inputs and outputs.

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Datasheet Details

Part number ICSSSTUAF32868A
Manufacturer IDT
File Size 569.76 KB
Description 28-BIT CONFIGURABLE REGISTERED BUFFER
Datasheet download datasheet ICSSSTUAF32868A Datasheet
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www.DataSheet4U.com DATASHEET 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 CONFIDENTIAL ICSSSTUAF32868A Description This 28-bit 1:2 configurable registered buffer is designed for 1.7V to 1.9V VDD operation. All inputs are compatible with the JEDEC standard for SSTL_18, except the chip-select gate-enable (CSGEN), control (C), and reset (RESET) inputs, which are LVCMOS. All outputs are edge-controlled circuits optimized for unterminated DIMM loads, and meet SSTL_18 specifications, except the open-drain error (QERR) output. The ICSSSTUAF32868A operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high and CLK going low. The device supports low-power standby operation.
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