* 28-bit 1:2 registered buffer with parity check functionality
* Supports SSTL_18 JEDEC specification on data inputs and outputs Applications
* DDR2 Memory M.

* DDR2 Memory Modules
* Provides complete DDR DIMM solution with ICS98ULPA877A or IDTCSPUA877A
* Supports L.

This 28-bit 1:2 configurable registered buffer is designed for 1.7V to 1.9V VDD operation. All inputs are compatible with the JEDEC standard for SSTL_18, except the chip-select gate-enable (CSGEN), control (C), and reset (RESET) inputs, which are LVC.

ICSSSTUAF32868A

ICSSSTUAF32865A

ICSSSTUAF32866B

ICSSSTUAF32866C

ICSSSTUAF32869A

ICSSSTUA32S869B

ICSSSTUAH32865A

ICSSSTUAH32868A

ICSSSTU32864

ICSSSTU32866

ICSSSTUB32864A

ICSSSTUB32866B

ICSSSTUB32871A