| Part number | ICSSSTUAF32868B |
|---|---|
| Datasheet | ICSSSTUAF32868B_IDT.pdf |
| File Size | 569.86 KB |
| Manufacturer | IDT |
| Description | 28-BIT CONFIGURABLE REGISTERED BUFFER |
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This 28-bit 1:2 configurable registered buffer is designed for 1.7V to 1.9V VDD operation. All inputs are patible with the JEDEC standard for SSTL_18, except the chip-select gate-enable (CSGEN), control (C), and reset (RESET) inputs, which are LVCMOS. All outputs are edge-controlled circuits optimized for unterminated DIMM loads, and meet SSTL_18 specifications, except the open-drain error (QERR) output.
| Part Number | Description |
|---|---|
| ICSSSTUAF32868A | 28-BIT CONFIGURABLE REGISTERED BUFFER |
| ICSSSTUAF32865A | 25-BIT CONFIGURABLE REGISTERED BUFFER |
| ICSSSTUAF32866B | 25-BIT CONFIGURABLE REGISTERED BUFFER |
| ICSSSTUAF32866C | 25-BIT CONFIGURABLE REGISTERED BUFFER |
| ICSSSTUAF32869A | 14-BIT CONFIGURABLE REGISTERED BUFFER |
| ICSSSTUAH32865A | 25-BIT CONFIGURABLE REGISTERED BUFFER |
| ICSSSTUAH32868A | 28-BIT CONFIGURABLE REGISTERED BUFFER |
| ICSSSTVA16859C | DDR 13-Bit to 26-Bit Registered Buffer |
| ICS1523 | Video Clock Synthesizer |
| ICS1526 | Video Clock Synthesizer |
