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ICSSSTUAF32869A - 14-BIT CONFIGURABLE REGISTERED BUFFER

Description

The ICSSSTUAF32869A is 14-bit 1:2 registered buffer with parity, designed for 1.7 V to 1.9 V VDD operation.

All clock and data inputs are compatible with the JEDEC standard for SSTL_18.

The control inputs are LVCMOS.

Features

  • 14-bit 1:2 registered buffer with parity check functionality.
  • Supports SSTL_18 JEDEC specification on data inputs and outputs.
  • 50% more dynamic driver strength than standard SSTU32864.
  • Supports LVCMOS switching levels on C1 and RESET inputs.
  • Low voltage operation: VDD = 1.7V to 1.9V.
  • Available in 150 BGA package.

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Datasheet Details

Part number ICSSSTUAF32869A
Manufacturer IDT
File Size 529.65 KB
Description 14-BIT CONFIGURABLE REGISTERED BUFFER
Datasheet download datasheet ICSSSTUAF32869A Datasheet
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www.DataSheet4U.com DATASHEET 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 ICSSSTUAF32869A The ICSSSTUAF32869A includes a parity checking function. The ICSSSTUAF32869A accepts a parity bit from the memory controller at its input pin PARIN one or two cycles after the corresponding data input, compares it with the data received on the D-inputs and indicates on its opendrain PTYERR pin (active low) whether a parity error has occurred. The number of cycles depends on the setting of C1. When used as a single device, the C1 input is tied low. When used in pairs, the C1 inputs is tied low for the first register (front) and the C1 input is tied high for the second register.
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