Datasheet Details
| Part number | IDT74SSTUAE32866A |
|---|---|
| Manufacturer | IDT |
| File Size | 666.82 KB |
| Description | 25-BIT CONFIGURABLE REGISTERED BUFFER |
| Datasheet | IDT74SSTUAE32866A_IDT.pdf |
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Overview: www.DataSheet4U.com DATASHEET 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 IDT74SSTUAE32866A outputs will remain low, thus ensuring no glitches on the output. The device monitors both DCS and CSR inputs and will gate the Qn outputs from changing states when both DCS and CSR inputs are high. If either DCS and CSR input is low, the Qn outputs will function normally. The RESET input has priority over the DCS and CSR control and will force the outputs low. If the DCS-control functionality is not desired, then the CSR input can be hardwired to ground, in which case, the setup-time requirement for DCS would be the same as for the other D data inputs. Package options include 96-ball LFBGA (MO-205CC).
| Part number | IDT74SSTUAE32866A |
|---|---|
| Manufacturer | IDT |
| File Size | 666.82 KB |
| Description | 25-BIT CONFIGURABLE REGISTERED BUFFER |
| Datasheet | IDT74SSTUAE32866A_IDT.pdf |
|
|
|
This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.425V to 1.575V VDD operation.
The control inputs are LVCMOS.
All outputs are 1.5-V CMOS drivers that have been optimized to drive the DDR-II DIMM load.
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| IDT74SSTUBF32866B | 25-BIT CONFIGURABLE REGISTERED BUFFER |
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