IS42S83200J Datasheet Text
IS42S83200J, IS42S16160J IS45S83200J, IS45S16160J
32Meg x 8, 16Meg x16 SEPTEMBER 2020 256Mb SYNCHRONOUS DRAM
Features
- Clock frequency: 166, 143, 133 MHz
- Fully synchronous; all signals referenced to a positive clock edge
- Internal bank for hiding row access/precharge
- Single Power supply: 3.3V + 0.3V
- LVTTL interface
- Programmable burst length
- (1, 2, 4, 8, full page)
- Programmable burst sequence:
Sequential/Interleave
- Auto Refresh (CBR)
- Self Refresh
- 8K refresh cycles every 32 ms (A2 grade) or
64 ms (mercial, industrial, A1 grade)
- Random column address every clock cycle
- Programmable CAS latency (2, 3 clocks)
- Burst read/write and burst read/single write operations capability
- Burst termination by burst stop and precharge mand
OPTIONS
- Package:
54-pin TSOP-II 54-ball BGA
- Operating Temperature Range: mercial (0oC to +70oC) Industrial (-40oC to +85oC) Automotive Grade A1 (-40oC to +85oC) Automotive Grade A2 (-40oC to +105oC)
OVERVIEW
ISSI's 256Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 256Mb SDRAM is organized as follows.
IS42/45S83200J IS42/45S16160J
8M x 8 x 4 Banks 4M x16x4 Banks
54-pin TSOPII 54-pin TSOPII
54-ball BGA...
