| Title | |
| Description | SEPTEMBER 2022 The IS43/46LR16128B/32640B is 2,147,483,648 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 128Meg words of 16bits or 64Meg words of 32bits. This product uses a double-data-rate architecture to achieve high-speed operation. The Data Input/ Output signals are transmitted on a 16-bit or 32-bit bus. The double data rate architecture is essentially a 2N pref... |
| Features |
• JEDEC standard 1.8V power supply. • VDD = 1.8V, VDDQ = 1.8V • Four internal banks for concurrent operation • MRS cycle with address key programs - CAS latency 2, 3 (clock) - Burst length (2, 4, 8) - Burst type (sequential & interleave) • Fully differential clock inputs (CK, /CK) • All inputs except data & DM are sampled at the rising edge of the ... |
| Datasheet |
 IS46LR32640B Datasheet - 2.70MB |
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