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IS61DDP2B21M36C - 36Mb DDR-IIP CIO SYNCHRONOUS SRAM

This page provides the datasheet information for the IS61DDP2B21M36C, a member of the IS61DDP2B22M18C 36Mb DDR-IIP CIO SYNCHRONOUS SRAM family.

Description

1Mx36 and 2Mx18 configuration available.

Common I/O read and write ports.

Max.

Synchronous pipeline read with self-timed late write operation.

Double Data Rate (DDR) interface for read and write input ports.

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Datasheet Details

Part number IS61DDP2B21M36C
Manufacturer ISSI
File Size 852.80 KB
Description 36Mb DDR-IIP CIO SYNCHRONOUS SRAM
Datasheet download datasheet IS61DDP2B21M36C Datasheet
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Full PDF Text Transcription

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IS61DDP2B22M18C/C1/C2 IS61DDP2B21M36C/C1/C2 2Mx18, 1Mx36 36Mb DDR-IIP (Burst 2) CIO SYNCHRONOUS SRAM (2.0 Cycle Read Latency) JANUARY 2017 FEATURES DESCRIPTION  1Mx36 and 2Mx18 configuration available.  Common I/O read and write ports.  Max. 500 MHz clock for high bandwidth  Synchronous pipeline read with self-timed late write operation.  Double Data Rate (DDR) interface for read and write input ports. The 36Mb IS61DDP2B21M36C/C1/C2 and IS61DDP2B22M18C/C1/C2 are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have a common I/O bus. The rising edge of K clock initiates the read/write operation, and all internal operations are selftimed.
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