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IS61NVP102418B - 18Mb STATE BUS SYNCHRONOUS SRAM

Download the IS61NVP102418B datasheet PDF. This datasheet also covers the IS61NLP51236B variant, as both devices belong to the same 18mb state bus synchronous sram family and are provided as variant models within a single manufacturer datasheet.

Description

The 18Meg product family

Features

  • 100 percent bus utilization.
  • No wait cycles between Read and Write.
  • Internal self-timed write cycle.
  • Individual Byte Write Control.
  • Single R/W (Read/Write) control pin.
  • Clock controlled, registered address, data and control.
  • Interleaved or linear burst sequence control using MODE input.
  • Three chip enables for simple depth expansion and address pipelining.
  • Power Down mode.
  • Common data inputs and data output.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS61NLP51236B-ISSI.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
IS61NVP102436A 36Mb STATE BUS SRAM Integrated Silicon Solution
IS61NVP204818A 36Mb STATE BUS SRAM Integrated Silicon Solution
IS61NVP204836B PIPELINE (NO WAIT) STATE BUS SRAM Integrated Silicon Solution
IS61NVP409618B PIPELINE (NO WAIT) STATE BUS SRAM Integrated Silicon Solution
IS61NVF102418 STATE BUS SRAM Integrated Silicon Solution

Other Datasheets by ISSI (now Infineon)

Part Number Description
IS61NVP102418 (IS61NVPxxxxx) STATE BUS SRAM
IS61NVP10018 (IS61NVP10018 / IS61NVP51236) State Bus SRAM
IS61NVP12818A (IS61NVPxxxxxA) STATE BUS SRAM
IS61NVP12836A (IS61NVPxxxxxA) STATE BUS SRAM
IS61NVP25618A (IS61NVPxxxxxA) STATE BUS SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B 512K x36 and 1024K x18 18Mb, PIPELINE 'NO WAIT' STATE BUS SYNCHRONOUS SRAM AUGUST 2019 FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control using MODE input • Three chip enables for simple depth expansion and address pipelining • Power Down mode • Common data inputs and data outputs • /CKE pin to enable clock and suspend operation • JEDEC 100-pin QFP, 165-ball BGA and 119- ball BGA packages • Power supply: NLP: VDD 3.3V (± 5%), VDDQ 3.3V/2.
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