IS61NVP204818A - 36Mb STATE BUS SRAM

Integrated Silicon Solution

IS61NVP204818A Datasheet Preview — Preview of IS61NVP204818A PDF

Datasheet Details

Part number	IS61NVP204818A
Manufacturer	Integrated Silicon Solution
File Size	168.59 KB
Description	36Mb STATE BUS SRAM
Datasheet	IS61NVP204818A_IntegratedSiliconSolution.pdf

IS61NVP204818A Product details

Description

The 36 Meg 'NLP/NVP' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications.

Features

100 percent bus utilization.
No wait cycles between Read and Write.
Internal self-timed write cycle.
Individual Byte Write Control.
Single R/W (Read/Write) control pin.
Clock controlled, registered address, data and control.
Interleaved or linear burst sequence control using MODE input.
Three chip enables for simple depth expansion and address pipelining.
Power Down mode.
Common data inputs and data output.

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Published: Mar 24, 2010 |