IS61NVP10018 - (IS61NVP10018 / IS61NVP51236) State Bus SRAM

ISSI

IS61NVP10018 Datasheet Preview — Preview of IS61NVP10018 PDF

Datasheet Details

Part number	IS61NVP10018
Manufacturer	ISSI
File Size	149.91 KB
Description	(IS61NVP10018 / IS61NVP51236) State Bus SRAM
Datasheet	IS61NVP10018_ISSI.pdf

IS61NVP10018 Product details

Description

® PRELIMINARY INFORMATION SEPTEMBER 2002 The 18 Meg 'NVP' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for network and communications customers.They are organized as 524, 288 words by 36 bits and 1M words by 18 bits, fabricated with ISSI's advanced CMOS technology.Incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read.Thi

Features

100 percent bus utilization.
No wait cycles between Read and Write.
Internal self-timed write cycle www. DataSheet4U. com.
Individual Byte Write Control.
Single R/W (Read/Write) control pin.
Clock controlled, registered address, data and control.
Interleaved or linear burst sequence control using MODE input.
Three chip enables for simple depth expansion and address pipelining for TQFP.
Power Down mode.
Commo.

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Published: Jul 12, 2008 |