* DESCRIPTION
* 100 percent bus utilization
* No wait cycles between Read and Write
* Internal self-timed write cycle
* Individual Byte Write Control
* Single Read/Write control pin
* Clock controlled, registered address, data and control
* Int
IS61NVF51236 Datasheet (496.97 KB)
IS61NVF51236
Integrated Silicon Solution
496.97 KB
State bus sram.
IS61NLF25672/IS61NVF25672 IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
256K x 72, 512K x 36 and 1M x 18
NOVEMBER 2013
18Mb, FLOW THROUGH.
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