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IS61NVF51236 - STATE BUS SRAM

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IS61NVF51236 Product details

Description

100 percent bus utilization No wait cycles between Read and Write Internal self-timed write cycle Individual Byte Write Control Single Read/Write control pin Clock controlled, registered address, data and control Interleaved or linear burst sequence control us- ing MODE input Three chip enables for simple depth expansion and address pipelining Power Down mode Common data inputs and data outputs

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