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IS61QDPB22M18A2 Datasheet 36Mb QUADP (Burst 2) Synchronous SRAM

Manufacturer: ISSI (now Infineon)

Overview: IS61QDPB22M18A/A1/A2 IS61QDPB21M36A/A1/A2 2Mx18, 1Mx36 36Mb QUADP (Burst 2) Synchronous SRAM (2.

Download the IS61QDPB22M18A2 datasheet PDF. This datasheet also includes the IS61QDPB22M18A variant, as both parts are published together in a single manufacturer document.

General Description

The and are synchronous, high- performance CMOS static random access memory (SRAM) devices.

These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround.

The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed.

Key Features

  • 1Mx36 and 2Mx18 configuration available.
  • On-chip Delay-Locked Loop (DLL) for wide data valid window.
  • Separate independent read and write ports with concurrent read and write operations.
  • Synchronous pipeline read with EARLY write operation.
  • Double Data Rate (DDR) interface for read and write input ports.
  • 2.5 Cycle read latency.
  • Fixed 2-bit burst for read and write operations.
  • Clock stop support.
  • Two input clocks (K and K#) for address and cont.