* G = Gate, S = Source, D = Drain, TAB = Drain G D S é (TAB)
* International standard package
* Low R HDMOS process
* Rugged polysilicon gate cell structure
* High commutating dv/dt rating
* Fast switching times TM DS (on) JEDEC TO-247 AD Mounting torque 1.
IXFJ36N30 Datasheet (99.87 KB)
IXFJ36N30
IXYS
99.87 KB
Power mosfet.
ADVANCE TECHNICAL INFORMATION HiPerFETTM N-Channel Enhancement Mode IXTJ 36N20 VDSS = 200 ID25 = RDS(on) = V 36 A 70 mΩ trr < 200 ns Symbol VDSS .
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