IXFJ40N30 Datasheet | IXYS

Hi Per FETTM Power MOSFETs N-Channel Enhancement Mode High dv/dt, Low trr, HDMOSTM Family Preliminary data sheet IXFJ 40N30 VDSS = 300 ID25 = RDS(on) = V 40 A 80 m W trr < 200 ns Symbol VDSS VDGR VGS VGSM ID25 IDM IAR EAR dv/dt PD TJ TJM Tstg TL Weight Test Conditions T J = 25°C to 150°C T J = 25°C to 150°C; RGS = 1 MW Continuous Transient TC = 25°C TC = 25°C, pulse width limited by TJM TC = 25°C TC = 25°C IS £ IDM, di/dt £ 100 A/ms, VDD £ VDSS, T J £ 150°C, RG = 2 W TC = 25°C Maximum Ratings 300 300 ±20 ±30 40 160 40 30 5 300 -55 ... +150 150 -55 ... +150 V V V V A A A m J V/ns W °C °C °C °C g Features G = Gate, S = Source, D = Drain, TAB = Drain G D S é (TAB) - Low profile, high power package - Long creep and strike distances - Easy up-grade path for TO-220 - Low RDS (on) HDMOSTM process - Rugged polysilicon gate cell structure - Unclamped Inductive Switching (UIS) - Low package inductance - Fast intrinsic Rectifier Applications - easy to drive and to protect rated designs 1.6 mm (0.062 in.) from case for 10 s 300 5 Symbol Test Conditions Characteristic Values (TJ = 25°C, unless otherwise specified) min. typ. max. 300 2 4 ±100 TJ = 25°C TJ = 125°C 200 1 V V n A m A m A - - - - - -...