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Integrated Circuit Systems

ICS93716YG-T Datasheet Preview

ICS93716YG-T Datasheet

Low Cost DDR Phase Lock Loop Clock Driver

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Integrated
Circuit
Systems, Inc.
ICS9371 6
Low Cost DDR Phase Lock Loop Clock Driver
Recommended Application:
DDR Clock Driver
Product Description/Features:
• Low skew, low jitter PLL clock driver
• I2C for functional and output control
• Feedback pins for input to output synchronization
• Spread Spectrum tolerant inputs
Switching Characteristics:
• PEAK - PEAK jitter (66MHz): <120ps
• PEAK - PEAK jitter (>100MHz): <75ps
• CYCLE - CYCLE jitter (>100MHz):<65ps
• OUTPUT - OUTPUT skew: <100ps
• Output Rise and Fall Time: 650ps - 950ps
Pin Configuration
CLKC0
CLKT0
VDD
CLKT1
CLKC1
GND
SCLK
CLK_INT
CLK_INC
VDDA
GND
VDD
CLKT2
CLKC2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 GND
27 CLKC5
26 CLKT5
25 CLKC4
24 CLKT4
23 VDD
22 SDATA
21 FBINC
20 FBINT
19 FB_OUTT
18 FB_OUTC
17 CLKT3
16 CLKC3
15 GND
28-Pin SSOP and TSSOP
Block Diagram
Functionality
AVDD
2.5V
(nom)
2.5V
(nom)
2.5V
(nom)
GND
GND
INPUTS
CLK_INT CLK_INC
LH
HL
<20MHz
LH
HL
CLKT
L
H
Z
L
H
OUTPUTS
CLKC FB_OUTT
HL
LH
ZZ
HL
LH
PLL State
FB_OUTC
H on
L on
Z off
H Bypassed/off
L Bypassed/off
SCLK
SDATA
Control
Logic
FB_INT
FB_INC
CLK_INC
CLK_INT
PLL
0420E—04/01/03
FB_OUTT
FB_OUTC
CLKT0
CLKC0
CLKT1
CLKC1
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
CLKT5
CLKC5




Integrated Circuit Systems

ICS93716YG-T Datasheet Preview

ICS93716YG-T Datasheet

Low Cost DDR Phase Lock Loop Clock Driver

No Preview Available !

ICS9371 6
Pin Descriptions
PIN NUMBER
PIN NAME
6, 11, 15, 28 GND
27, 25, 16, 14, 5, 1 CLKC(5:0)
26, 24, 17, 13, 4, 2 CLKT(5:0)
3, 12, 23
VDD
7 SCLK
8 CLK_INT
9 CLK_INC
10 VDDA
18 FB_OUTC
19 FB_OUTT
20 FB_INT
21 FB_INC
22 SDATA
TYPE
DESCRIPTION
PWR Ground
OUT "Complementary" clocks of differential pair outputs.
OUT "True" Clock of differential pair outputs.
PWR Power supply 2.5V
IN Clock input of I2C input, 5V tolerant input
IN "True" reference clock input
IN "Complementary" reference clock input
PWR
OUT
OUT
IN
IN
IN
Analog power supply, 2.5V
"Complementary" Feedback output, dedicated for external feedback. It
switches at the same frequency as the CLK. This output must be wired
to FB_INC.
"True" " Feedback output, dedicated for external feedback. It switches
at the same frequency as the CLK. This output must be wired to
FB_INT.
"True" Feedback input, provides feedback signal to the internal PLL for
synchronization with CLK_INT to eliminate phase error.
"Complementary" Feedback input, provides signal to the internal PLL
for synchronization with CLK_INC to eliminate phase error.
Data input for I2C serial input, 5V tolerant input
0420E—04/01/03
2



Part Number ICS93716YG-T
Description Low Cost DDR Phase Lock Loop Clock Driver
Maker Integrated Circuit Systems
Total Page 12 Pages
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