ICS93732 Datasheet - Renesas

ICS93732 Low Cost DDR Phase Lock Loop Zero Delay Buffer

ICS93732 Features

* Low skew, low jitter PLL clock driver

* Max frequency supported = 266MHz (DDR 533)

* I2C for functional and output control

* Feedback pins for input to output synchronization

* Spread Spectrum tolerant inputs

* 3.3V tolerant CLK_INT input Switching

Datasheet Details

ICS93732

276.98 KB

Low cost ddr phase lock loop zero delay buffer.

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