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8T73S208 - Differential LVPECL Clock Divider and Fanout Buffer

Description

The 8T73S208 is a high-performance differential LVPECL clock divider and fanout buffer.

The device is designed for the frequency division and signal fanout of high-frequency, low phase-noise clocks.

The 8T73S208 is characterized to operate from a 2.5V and 3.3V power supply.

Features

  • One differential input reference clock.
  • Differential pair can accept the following differential input levels: LVDS, LVPECL, CML.
  • Integrated.

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Datasheet Details

Part number 8T73S208
Manufacturer Integrated Device Technology
File Size 377.22 KB
Description Differential LVPECL Clock Divider and Fanout Buffer
Datasheet download datasheet 8T73S208 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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2.5 V, 3.3 V Differential LVPECL Clock Divider and Fanout Buffer 8T73S208 Datasheet General Description The 8T73S208 is a high-performance differential LVPECL clock divider and fanout buffer. The device is designed for the frequency division and signal fanout of high-frequency, low phase-noise clocks. The 8T73S208 is characterized to operate from a 2.5V and 3.3V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8T73S208 ideal for those clock distribution applications demanding well-defined performance and repeatability. The integrated input termination resistors make interfacing to the reference source easy and reduce passive component count.
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