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ICS8543I - Differential-to-LVDS Fanout Buffer

General Description

The ICS8543I is a low skew, high performance 1-to-4 Differential-to-LVDS Clock Fanout Buffer.

Utilizing Low Voltage Differential Signaling (LVDS) the ICS8543I provides a low power, low noise, solution for distributing clock signals over controlled impedances of 100.

Key Features

  • Four differential LVDS output pairs.
  • Selectable differential CLK/nCLK or LVPECL clock inputs.
  • CLK/nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL.
  • PCLK/nPCLK pair can accept the following differential input levels: LVPECL, CML, SSTL.
  • Maximum output frequency: 650MHz.
  • Translates any single-ended input signals to LVDS levels with resistor bias on nCLK input.
  • Additive phase Jitter, RMS: 0.

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Datasheet Details

Part number ICS8543I
Manufacturer Integrated Device Technology
File Size 209.47 KB
Description Differential-to-LVDS Fanout Buffer
Datasheet download datasheet ICS8543I Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Low Skew, 1-to-4, Differential-to-LVDS Fanout Buffer ICS8543I DATA SHEET General Description The ICS8543I is a low skew, high performance 1-to-4 Differential-to-LVDS Clock Fanout Buffer. Utilizing Low Voltage Differential Signaling (LVDS) the ICS8543I provides a low power, low noise, solution for distributing clock signals over controlled impedances of 100. The ICS8543I has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin.