IS61DDB21M18A Datasheet 18Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM

Manufacturer: ISSI (now Infineon)

Datasheet Details

Part number	IS61DDB21M18A
Manufacturer	ISSI (now Infineon)
File Size	589.81 KB
Description	18Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM
Download	IS61DDB21M18A Download (PDF)

The 18Mb IS61DDB251236A and IS61DDB21M18A are synchronous, high-performance CMOS static random access memory (SRAM) devices.

These SRAMs have a common I/O bus.

The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed.

IS61DDB21M18A IS61DDB251236A 1Mx18, 512Kx36 18Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM OCTOBER.

512Kx36 and 1Mx18 configuration available.
On-chip delay-locked loop (DLL) for wide data valid window.
Common I/O read and write ports.
Synchronous pipeline read with self-timed late write operation.
Double Data Rate (DDR) interface for read and write input ports.
Fixed 2-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K#) for address and control registering at rising edges only.
Two input clocks (C and C#.

Part Number	Description
IS61DDB21M36	DDR-II (Burst of 2) CIO Synchronous SRAMs
IS61DDB21M36A	36Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM
IS61DDB22M18	DDR-II (Burst of 2) CIO Synchronous SRAMs
IS61DDB22M18A	36Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM
IS61DDB22M36	DDR-II (Burst of 2) CIO Synchronous SRAMs
IS61DDB22M36A	72Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM
IS61DDB24M18	DDR-II (Burst of 2) CIO Synchronous SRAMs
IS61DDB24M18A	72Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM
IS61DDB251236A	18Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM
IS61DDB41M18A	18Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM