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IS61DDSB21M36A Datasheet 36Mb DDR-II (Burst 2) SIO SYNCHRONOUS SRAM

Manufacturer: ISSI (now Infineon)

Download the IS61DDSB21M36A datasheet PDF. This datasheet also includes the IS61DDSB22M18A variant, as both parts are published together in a single manufacturer document.

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Note: The manufacturer provides a single datasheet file (IS61DDSB22M18A-IntegratedSiliconSolution.pdf) that lists specifications for multiple related part numbers.

General Description

The 36Mb IS61DDSB21M36A and IS61DDSB22M18A are synchronous, high-performance CMOS static random access memory (SRAM) devices.

These SRAMs have a separate I/O bus.

The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed.

Overview

IS61DDSB22M18A IS61DDSB21M36A 2Mx18, 1Mx36 36Mb DDR-II (Burst 2) SIO SYNCHRONOUS SRAM JANUARY.

Key Features

  • 1Mx36 and 2Mx18 configuration available.
  • On-chip delay-locked loop (DLL) for wide data valid window.
  • Seperate I/O read and write ports.
  • Synchronous pipeline read with self-timed late write operation.
  • Double Data Rate (DDR) interface for read and write input ports.
  • Fixed 2-bit burst for read and write operations.
  • Clock stop support.
  • Two input clocks (K and K#) for address and control registering at rising edges only.
  • Two input clocks (C and C#.

More Datasheets from ISSI (now Infineon)

Part Number Description
IS61DDSB22M18A 36Mb DDR-II (Burst 2) SIO SYNCHRONOUS SRAM
IS61DDB21M18A 18Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM
IS61DDB21M36 DDR-II (Burst of 2) CIO Synchronous SRAMs
IS61DDB21M36A 36Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM
IS61DDB22M18 DDR-II (Burst of 2) CIO Synchronous SRAMs
IS61DDB22M18A 36Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM
IS61DDB22M36 DDR-II (Burst of 2) CIO Synchronous SRAMs
IS61DDB22M36A 72Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM
IS61DDB24M18 DDR-II (Burst of 2) CIO Synchronous SRAMs
IS61DDB24M18A 72Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM