N0072S Datasheet - InterFET

Process Geometry

* Low Noise: 2.0 nV/√Hz Typical

* Typical Input Capacitance: 6.5pF

* Typical Breakdown Voltage: -45V

* Small Die: 467um X 467um X 203um

* Bond Pads: 90um X 90um

* Substrate Connected to Gate

* Au Back-Side Finish Applications

* Low Nois

N0072S

InterFET

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Process geometry.

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N0072S Process Geometry InterFET

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