• Part: CD4027BMS
  • Description: CMOS Dual J-K Master-Slave Flip-Flop
  • Manufacturer: Intersil
  • Size: 72.40 KB
Download CD4027BMS Datasheet PDF
Intersil
CD4027BMS
Features - High Voltage Type (20V Rating) - Set - Reset Capability - Static Flip-Flop Operation - Retains State Indefinitely with Clock Level Either “High” or “Low” - Medium Speed Operation - 16MHz (typ.) Clock Toggle Rate at 10V - Standardized Symmetrical Output Characteristics - 100% Tested For Quiescent Current at 20V - Maximum Input Current of 1µA at 18V Over Full Package-Temperature Range; - 100n A at 18V and +25o C - Noise Margin (Over Full Package Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V - 5V, 10V and 15V Parametric Ratings - Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” Q2 1 Q2 2 CLOCK 2 3 RESET 2 4 K2 5 J2 6 SET 2 7 VSS 8 16 VDD 15 Q1 14 Q1 13 CLOCK 1 12 RESET 1 11 K1 10 J1 9 SET 1 Functional Diagram SET 1 9 VDD 16 J1 10 K1 11 CLOCK1 13 F/F1 15 Q1 14 Q1 Applications - Registers, Counters, Control Circuits RESET1 12 SET2 J2 K2 7 6 5 3 F/F2 2 Q2 1...