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MR45V200A Datasheet Preview

MR45V200A Datasheet

FeRAM

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MR45V200A
FEDR45V200A-01
Issue Date: Jan. 31, 2014
2M(262,144-Word 8-Bit) FeRAM (Ferroelectric Random Access Memory) SPI
GENERAL DESCRIPTION
The MR45V200A is a nonvolatile 262,144-word x 8-bit ferroelectric random access memory (FeRAM)
developed in the ferroelectric process and silicon-gate CMOS technology. The MR45V200A is accessed using
Serial Peripheral Interface.Unlike SRAMs, this device, whose cells are nonvolatile, eliminates battery backup
required to hold data. This device has no mechanisms of erasing and programming memory cells and blocks,
such as those used for various EEPROMs. Therefore, the write cycle time can be equal to the read cycle time and
the power consumption during a write can be reduced significantly.
The MR45V200A can be used in various applications, because the device is guaranteed for the write/read
tolerance of 1012 cycles per bit and the rewrite count can be extended significantly.
FEATURES
• 262,144-word 8-bit configuration (Serial Peripheral Interface : SPI)
• A single 2.7V to 3.6V power supply
• Operating frequency:
• Read/write tolerance
34MHz
1012 cycles/bit
• Data retention
10 years
• Guaranteed operating temperature range
40 to 85C (Extended temperature version)
• Package options:
8-pin plastic DIP
1/17




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MR45V200A Datasheet Preview

MR45V200A Datasheet

FeRAM

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PIN CONFIGURATION
FEDR45V200A-01
MR45V200A
8-pin plastic DIP
CS#
SO
WP#
VSS
1
2
3
4
8 VCC
7 HOLD#
6 SCK
5 SI
Note:
Signal names that end with # indicate that the signals are negative-true logic.
PIN DESCRIPTIONS
Pin Name
Description
Chip Select (input, negative logic)
CS# Latches an address by low input, activates the FeRAM, and enables a read or write
operation.
WP#
Write Protect( input , negative logic )
Write Protect pin controls write-operation to the status-register(BP0,BP1). This pin should
be fixed low or high in write-operations.
HOLD( input , negative logic )
HOLD#
Hold pin is used when the serial-communication suspended without disable the chip
select. When HOLD# is low ,the serial-output is in High-Z status and
serial-input/serial-clock are “Don’t Care” . CS# should be low in hold operation.
SCK
Serial Clock
Serial Clock is the clock input pin for setting for serial data timing. Inputs are latched on
the rising edge and output occur on the falling edge.
SI
Serial input
SI pins are serial input pins for Operation-code , addresses ,and data-inputs .
SO Serial output
SO pins are serial output pins.
VCC, VSS
Power supply
Apply the specified voltage to VCC. Connect VSS to ground.
2/17


Part Number MR45V200A
Description FeRAM
Maker LAPIS
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