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MACRONIX

MX25L12850F Datasheet Preview

MX25L12850F Datasheet

CMOS MXSMIO RPMC FLASH MEMORY

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MX25L12850F
MX25L12850F
3V, 128M-BIT [x 1/x 2/x 4]
CMOS MXSMIO® (SERIAL MULTI I/O)
RPMC FLASH MEMORY




MACRONIX

MX25L12850F Datasheet Preview

MX25L12850F Datasheet

CMOS MXSMIO RPMC FLASH MEMORY

No Preview Available !

MX25L12850F
Contents
1. FEATURES............................................................................................................................................................... 4
2. GENERAL DESCRIPTION...................................................................................................................................... 6
3. PIN CONFIGURATIONS .......................................................................................................................................... 7
4. PIN DESCRIPTION................................................................................................................................................... 7
5. BLOCK DIAGRAM.................................................................................................................................................... 8
6. DATA PROTECTION................................................................................................................................................. 9
Table 1. Protected Area Sizes....................................................................................................................10
Table 2. 4K-bit Secured OTP Definition..................................................................................................... 11
7. Memory Organization............................................................................................................................................ 12
Table 3. Memory Organization...................................................................................................................12
8. DEVICE OPERATION............................................................................................................................................. 13
9. COMMAND DESCRIPTION.................................................................................................................................... 15
Table 4. Command Set...............................................................................................................................15
9-1. Write Enable (WREN)............................................................................................................................... 19
9-2. Write Disable (WRDI)................................................................................................................................ 20
9-3. Read Identification (RDID)........................................................................................................................ 21
Table 5. ID Definitions ...............................................................................................................................21
9-4. Release from Deep Power-down (RDP), Read Electronic Signature (RES)............................................ 22
9-5. Read Electronic Manufacturer ID & Device ID (REMS)............................................................................ 24
9-6. Read Status Register (RDSR).................................................................................................................. 25
9-7. Read Configuration Register (RDCR)....................................................................................................... 26
Table 6. Configuration Register Table........................................................................................................30
9-8. Write Status Register (WRSR).................................................................................................................. 31
Table 7. Protection Modes..........................................................................................................................32
9-9. Read Data Bytes (READ)......................................................................................................................... 34
9-10. Read Data Bytes at Higher Speed (FAST_READ)................................................................................... 35
9-11. Dual Output Read Mode (DREAD)........................................................................................................... 36
9-12. 2 x I/O Read Mode (2READ).................................................................................................................... 37
9-13. Quad Read Mode (QREAD)..................................................................................................................... 38
9-14. 4 x I/O Read Mode (4READ).................................................................................................................... 39
9-15. Performance Enhance Mode.................................................................................................................... 40
9-16. Performance Enhance Mode Reset ......................................................................................................... 42
9-17. Sector Erase (SE)..................................................................................................................................... 43
9-18. Block Erase (BE32K)................................................................................................................................ 44
9-19. Block Erase (BE)...................................................................................................................................... 45
9-20. Chip Erase (CE)........................................................................................................................................ 46
9-21. Page Program (PP).................................................................................................................................. 47
9-22. 4 x I/O Page Program (4PP)..................................................................................................................... 48
9-23. Deep Power-down (DP)............................................................................................................................ 49
9-24. Enter Secured OTP (ENSO)..................................................................................................................... 50
9-25. Exit Secured OTP (EXSO)........................................................................................................................ 50
P/N: PM2039
REV. 1.0, DEC. 08, 2014
2


Part Number MX25L12850F
Description CMOS MXSMIO RPMC FLASH MEMORY
Maker MACRONIX
Total Page 30 Pages
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