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Micrel Semiconductor

SY89875U Datasheet Preview

SY89875U Datasheet

IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER AND 1:2 FANOUT BUFFER

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Micrel, Inc.
2.5V, 2.0GHz ANY DIFF. IN-TO-LVDS
Precision Edge®
Precision ESdY8g9e8®75U
PROGRAMMABLE CLOCK DIVIDER AND 1:2
SY89875U
FANOUT BUFFER W/ INTERNAL TERMINATION
FEATURES
„ Integrated programmable clock divider and 1:2
fanout buffer
„ Guaranteed AC performance over temperature and
voltage:
• > 2.0GHz fMAX
• < 200ps tr/tf
• < 15ps within device skew
„ Low jitter design:
• < 10psPP total jitter
• < 1psRMS cycle-to-cycle jitter
„ Unique input termination and VT Pin for DC-coupled
and AC-coupled Inputs; CML, PECL, LVDS and
HSTL
„ LVDS compatible outputs
„ TTL/CMOS inputs for select and reset
„ Parallel programming capability
„ Programmable divider ratios of 1, 2, 4, 8 and 16
„ Low voltage operation 2.5V
„ Output disable function
„ –40°C to 85°C temperature range
„ Available in 16-pin (3mm x 3mm) MLF® package
APPLICATIONS
„ SONET/SDH line cards
„ Transponders
„ High-end, multiprocessor servers
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION
This low-skew, low-jitter device is capable of accepting a
high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDS
or HSTL clock input signal and dividing down the frequency
using a programmable divider to create a lower speed
version of the input clock. Available divider ratios are 2, 4, 8
and 16, or straight pass-through.
The differential input buffer has a unique internal
termination design that allows access to the termination
network through a VT pin. This feature allows the device to
easily interface to different logic standards. A VREF-AC
reference is included for AC-coupled applications.
The /RESET input asynchronously resets the divider. In
the pass-through function (divide by 1) the /RESET
synchronously enables or disables the outputs on the next
falling edge of IN (rising edge of /IN).
TYPICAL PERFORMANCE
OC-12 to OC-3
Translator/Divider
CML/LVPECL/LVDS
622MHz
Clock In
Divide-by-4
LVDS
155.5MHz
Clock Out
S2
/RESET
Enable
FF
Enable
MUX
IN
950
VT
950
/IN
S1
S0
Decoder
Divided
by
2, 4, 8
or 16
MUX
Q0
/Q0
Q1
/Q1
VREF_AC
United States Patent No. RE44,134
Precision Edge is a registered trademark of Micrel, Inc.
MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
1
IN
/IN
Q0
/Q0
622MHz In
155.5MHz Out
Rev.: D Amendment: /0
Issue Date: August 2007




Micrel Semiconductor

SY89875U Datasheet Preview

SY89875U Datasheet

IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER AND 1:2 FANOUT BUFFER

No Preview Available !

Micrel, Inc.
Precision Edge®
SY89875U
PACKAGE/ORDERING INFORMATION
16 15 14 13
Q0 1
/Q0 2
Q1 3
/Q1 4
12 IN
11 VT
10 VREF-AC
9 /IN
5678
16-Pin MLF® (MLF-16)
Ordering Information(1)
Part Number
Package Operating
Type
Range
Package
Marking
Lead
Finish
SY89875UMI
SY89875UMITR(2)
SY89875UMG(3)
MLF-16
MLF-16
MLF-16
SY89875UMGTR(2, 3) MLF-16
Industrial
Industrial
Industrial
Industrial
875U
875U
875U with
Pb-Free bar line indicator
875U with
Pb-Free bar line indicator
Sn-Pb
Sn-Pb
NiPdAu
Pb-Free
NiPdAu
Pb-Free
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.
2. Tape and Reel.
3. Pb-Free package is recommended for new designs.
PIN DESCRIPTION
Pin Number
12, 9
1, 2, 3, 4
16, 15, 5
6
8
10
11
7, 14
13
Pin Name
IN, /IN
Q0, /Q0
Q1, /Q1
S0, S1, S2
NC
/RESET,
/DISABLE
VREF-AC
VT
VCC
GND
Exposed
Pin Function
Differential Input: Internal 50ý termination resistors to VT input. Flexible input accepts any
differential input. See “Input Interface Applications” section.
Differential Buffered LVDS Outputs: Divided by 1, 2, 4, 8 or 16. See “Truth Table.”
Unused output pairs must be terminated with 100ý across the different pair.
Select Pins: See “Truth Table.” LVTTL/CMOS logic levels. Internal 25ký pull-up resistor.
Logic HIGH if left unconnected (divided by 16 mode.) Input threshold is VCC/2.
No Connect.
LVTTL/CMOS Logic Levels: Internal 25ký pull-up resistor. Logic HIGH if left unconnected.
Apply LOW to reset the divider (divided by 2, 4, 8 or 16 mode). Also acts as a disable/enable
function. The reset and disable function occurs on the next high-to-low clock input transition.
Input threshold is VCC/2.
Reference Voltage: Equal to VCC–1.4V (approx.). Used for AC-coupled applications only.
Decouple the VREF–AC pin with a 0.01µF capacitor. See “Input Interface Applications” section.
Termination Center-Tap: For CML or LVDS inputs, leave this pin floating. Otherwise, See
Figures 4a to 4f, “Input Interface Applications” section.
Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitor.
Ground. Exposed pad must be connected to the same potential as the GND pin.
TRUTH TABLE
/RESET(1) S2 S1 S0 Outputs
1 0 X X Reference Clock (pass through)
1 1 0 0 Reference Clock ÷2
1 1 0 1 Reference Clock ÷4
1 1 1 0 Reference Clock ÷8
1 1 1 1 Reference Clock ÷16
0(1) X X X Q = LOW, /Q = HIGH
Clock Disable
Note 1. Reset/Disable function is asserted on the next clock input
(IN, /IN) high-to-low transition.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
2


Part Number SY89875U
Description IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER AND 1:2 FANOUT BUFFER
Maker Micrel Semiconductor
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Micrel Semiconductor





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