SY89875U buffer equivalent, in-to-lvds programmable clock divider and 1:2 fanout buffer.
* Integrated programmable clock divider and 1:2 fanout buffer
* Guaranteed AC performance over temperature and voltage:
* > 2.0GHz fMAX
* < 200ps tr/tf
* SONET/SDH line cards
* Transponders
* High-end, multiprocessor servers
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTI.
This low-skew, low-jitter device is capable of accepting a high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDS or HSTL clock input signal and dividing down the frequency using a programmable divider to create a lower speed version of the input cloc.
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