SY89875U
FEATURES
- Integrated programmable clock divider and 1:2 fanout buffer
- Guaranteed AC performance over temperature and voltage:
- > 2.0GHz f MAX
- < 200ps tr/tf
- < 15ps within device skew
- Low jitter design:
- < 10ps PP total jitter
- < 1ps RMS cycle-to-cycle jitter
- Unique input termination and VT Pin for DC-coupled and AC-coupled Inputs; CML, PECL, LVDS and HSTL
- LVDS patible outputs
- TTL/CMOS inputs for select and reset
- Parallel programming capability
- Programmable divider ratios of 1, 2, 4, 8 and 16
- Low voltage operation 2.5V
- Output disable function
- - 40°C to 85°C temperature range
- Available in 16-pin (3mm x 3mm) MLF® package
APPLICATIONS
- SONET/SDH line cards
- Transponders
- High-end, multiprocessor servers
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION
This low-skew, low-jitter device is capable of accepting a high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDS or HSTL clock input signal and dividing down the frequency using a programmable divider to create a lower speed...
