SY89876L termination equivalent, any differential in-to-lvds programmable clock divider and 1:2 fanout buffer w/ internal termination.
DESCRIPTION
* Integrated programmable clock divider and 1:2 This low-skew, low-jitter device is capable of accepting a fanout buffer high-speed (e.g., 622MHz or hig.
* Unique input termination and VT Pin for DC- and ACThe /RESET input asynchronously resets the divider. In coupled .
* Integrated programmable clock divider and 1:2 This low-skew, low-jitter device is capable of accepting a fanout buffer high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDS or HSTL clock input signal and dividing down the frequency
* Guara.
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