M2V12D20TP-10
Description
M2S12D20TP is a 4-bank x 33,554,432-word x 4-bit, M2S12D30TP is a 4-bank x 16,777,216-word x 8-bit, double data rate synchronous DRAM, with SSTL_2 interface.
Key Features
- All address and control input signals are sampled on the crossing of the positive edge of CLK and negative edge of /CLK
- Output (read) data is referenced to the crossings of CLK and /CLK (both directions of crossing)
- Clock Enable: CKE controls internal clock
- When CKE is low, internal clock for the following cycle is ceased
- CKE is also used to select auto / self refresh
- After self refresh mode is started, CKE bees asynchronous input
- Self refresh is maintained as long as CKE is low
- Chip Select: When /CS is high, any mand means No Operation
- bination of /RAS, /CAS, /WE defines basic mands
- A0-12 specify the Row / Column Address in conjunctio
