M2V28S20/30/40TP ITEM tCLK tRAS tRCD tAC tRC Icc1 Clock Cycle Time Row to Column Delay Access Time from CLK Ref/Active Command Period Operation Current (Max.) (Single Ban.

M2V28S20TP is organized as 4-bank x 8,388,608-word x 4-bit Synchronous DRAM with LVTTL interface and M2V28S30TP is organized as 4-bank x 4,194,304-word x 8-bit and M2V28S40TP is organized as 4-bank x 2,097,152-word x 16-bit. All inputs and outputs ar.

M2V28S40ATP

M2V28S20ATP

M2V28S20TP

M2V28S30ATP

M2V28S30TP

M2V28D20ATP-10

M2V28D20ATP-75

M2V28D30ATP-10

M2V28D30ATP-75

M2V28D40ATP-10

M2V28D40ATP-75

M2V12D20TP

M2V12D20TP-10