- Vdd=Vddq=2.5V+0.2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differenti.

M2S28D20ATP is a 4-bank x 8388608-word x 4-bit, M2S28D30ATP is a 4-bank x 4194304-word x 8-bit, M2S28D40ATP is a 4-bank x 2097152-word x 16-bit, double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced .

M2V28D30ATP-10

M2V28D20ATP-10

M2V28D20ATP-75

M2V28D40ATP-10

M2V28D40ATP-75

M2V28S20ATP

M2V28S20TP

M2V28S30ATP

M2V28S30TP

M2V28S40ATP

M2V28S40TP

M2V12D20TP

M2V12D20TP-10