MC100ES6130 driver equivalent, 2.5/3.3v 1:4 pecl clock driver.
a 2:1 input MUX which is ideal for redundant clock switchover applications. This device also includes a synchronous enable pin that forces the outputs into a fixed logic .
This device also includes a synchronous enable pin that forces the outputs into a fixed logic state. Enable or disable .
Number 1, 2, 3, 4, 5, 6, 7, 8 9 10 Name Q0 to Q3 Q0 to Q3 VEE IN_SEL Description LVPECL differential outputs: Terminate with 50Ω to VCC
–2V. For single-ended applications, terminate the unused output with 50Ω to VCC
–2V..
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