MC100ES7111 Datasheet | Motorola Semiconductor

Features : 1:10 differential clock fanout buffer 50 ps maximum device skew1 Si Ge technology Supports DC to 1000 MHz operation1 of clock or data signals LVDS patible differential clock outputs PECL and HSTL/LVDS patible differential clock inputs 3.3V power supply Supports industrial temperature range Standard 32 lead LQFP package FA SUFFIX 32- LEAD LQFP PACKAGE CASE 873A Functional Description The MC100ES7111 is designed for low skew clock distribution systems and supports clock frequencies up to 1000 MHz1. The device accepts two clock sources. The CLK0 input accepts LVDS or HSTL patible signals and CLK1 accepts PECL patible signals. The selected input signal is distributed to 10 identical, differential LVDS patible outputs. The output enable control is synchronized internally preventing output runt pulse generation. Outputs are only disabled or enabled when the outputs are already in logic low state (true outputs logic low, inverted outputs logic high). The internal synchronizer eliminates the setup and hold time requirements for the external clock enable signal. The device is packaged in a 7x7 mm2 32-lead LQFP package. This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. 1. AC specifications are design targets and subject to change © Motorola, Inc. 2002 .. Q3 Q3 Q4 Q4 Q5 Q5 Q6 18 Q6 17 16 15 14 13 VCC Q7 Q7 Q8 Q8 Q9 Q9 VCC 12 11 10 9 1 2 3 4 5 6 7 8 GND Q0 Q0 24 VCC Q2 Q2 Q1 Q1 Q0 Q0 VCC 25 26 27 28 CLK0 CLK0 0 1 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 OE Q5 Q5 Q6 Q6 Q7 Q7 Q8 Q8 Q9 Q9 29 30 31 32 CLK1 CLK1 CLK_SEL CLK_SEL CLK0 CLK0 CLK1 1 Figure 1. MC100ES7111 Logic Diagram Table 1. PIN CONFIGURATION Pin CLK0, CLK0 CLK1, CLK1 CLK_SEL OE Q[0- 9], Q[0- 9] GND VCC I/O Input Input Input Input Output Supply Supply Type HSTL/LVDS PECL LVCMOS LVCMOS LVDS Figure 2. 32- Lead Package Pinout (Top View) Function Differential HSTL...