MC88915TFN160 driver equivalent, low skew cmos pll clock driver.
* Five Outputs (Q0
–Q4) with Output
–Output Skew < 500 ps each being phase and frequency locked to the SYNC input
* The phase variat.
when a central system clock must be distributed synchronously to multiple boards (see Figure 7).
LOW SKEW CMOS PLL CLOC.
on page 11). Pulling the OE/RST pin low puts the clock outputs 2X_Q, Q0
–Q4, Q5 and Q/2 into a high impedance state (3
–state). After the OE/RST pin goes back high Q0
–Q4, Q5 and Q/2 will be reset in the l.
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