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MC88916 Datasheet

LOW SKEW CMOS PLL CLOCK DRIVER WITH PROCESSOR RESET

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MC88916 pdf
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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Low Skew CMOS PLL Clock
Driver With Processor Reset
MC88916
The MC88916 Clock Driver utilizes phase–locked loop technology to
lock its low skew outputs’ frequency and phase onto an input reference
clock. It is designed to provide clock distribution for CISC microprocessor
or single processor RISC systems. The RST_IN/RST_OUT(LOCK) pins
provide a processor reset function designed specifically for the
MC68/EC/LC030/040 microprocessor family. The 88916 comes in two
speed grades: 70 and 80MHz. These frequencies correspond to the
2X_Q maximum output frequency. The two grades should be ordered as
the MC88916DW70 and MC88916DW80, respectively.
LOW SKEW CMOS PLL
CLOCK DRIVER WITH
PROCESSOR RESET
Provides Performance Required to Drive 68030 Microprocessor Family
as well as the 33 and 40MHz 68040 Microprocessors
Three Outputs (Q0–Q2) With Output–Output Skew <500ps and Six
Outputs Total (Q0–Q2, Q3, 2X_Q,) With <1ns Skew Each Being Phase
and Frequency Locked to the SYNC Input
The Phase Variation From Part–to–Part Between SYNC and the ‘Q’
Outputs Is Less Than 600ps (Derived From the TPD Specification,
Which Defines the Part–to–Part Skew)
SYNC Input Frequency Range From 5MHZ to 2X_Q FMax/4
Additional Outputs Available at 2X and ÷2 the System ‘Q’ Frequency.
Also a Q (180° Phase Shift) Output Available.
All Outputs Have ±36mA Drive (Equal High and Low) CMOS Levels.
Can Drive Either CMOS or TTL Inputs. All Inputs Are TTL–Level
Compatible
Test Mode Pin (PLL_EN) Provided for Low Frequency Testing
20
1
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
The PLL allows the high current, low skew outputs to lock onto a single clock input and distribute it with essentially zero delay
to multiple locations on a board. The PLL also allows the MC88916 to multiply a low frequency input clock and distribute it locally
at a higher (2X) system frequency.
Three ‘Q’ outputs (Q0–Q2) are provided with less than 500ps skew between their rising edges. The Q3 output is inverted (180°
phase shift) from the ‘Q’ outputs. A 2X_Q output runs at twice the ‘Q’ output frequency. The 2X_Q output does not meet the
stringent duty cycle requirement of the 20 and 25Mhz 68040 microprocessor PCLK input. The 88920 has been designed
specifically to provide the 68040 PCLK and BCLK inputs for the low frequency 68040 microprocessor. 68040 designers should
refer to the 88920 data sheet for more details. For the 33 and 40MHz 68040, the 2X_Q output will meet the duty cycle
requirements of the PCLK input. The Q/2 output runs at 1/2 the ‘Q’ frequency. This output is fed back internally, providing a fixed
2X multiplication from the ‘Q’ outputs to the SYNC input. Since the feedback is done internally (no external feedback pin is
provided) the input/output frequency relationships are fixed.
In normal phase–locked operation the PLL_EN pin is held high. Pulling the PLL_EN pin low disables the VCO and puts the
88916 in a static ‘test mode’. In this mode there is no frequency limitation on the input clock, which is necessary for a low
frequency board test environment.
The RST_OUT(LOCK) pin doubles as a phase–lock indicator. When the RST_IN pin is held high, the open drain RST_OUT
pin will be pulled actively low until phase–lock is achieved. When phase–lock occurs, the RST_OUT(LOCK) is released and a
pull–up resistor will pull the signal high. To give a processor reset signal, the RST_IN pin is toggled low, and the
RST_OUT(LOCK) pin will stay low for 1024 cycles of the ‘Q’ output frequency after the RST_IN pin is brought back high.
Description of the RST_IN/RST_OUT(LOCK) Functionality
The RST_IN and RST_OUT(LOCK) pins provide a 68030/040 processor reset function, with the RST_OUT pin also acting as
a lock indicator. If the RST_IN pin is held high during system power–up, the RST_OUT pin will be in the low state until steady
state phase/frequency lock to the input reference is achieved. 1024 ‘Q’ output cycles after phase–lock is achieved the
RST_OUT(LOCK) pin will go into a high impedance state, allowing it to be pulled high by an external pull–up resistor (see the
AC/DC specs for the characteristics of the RST_OUT(LOCK) pin). If the RST_IN pin is held low during power–up, the
RST_OUT(LOCK) pin will remain low.
11/93
© Motorola, Inc. 1995
1
REV 2


Motorola Electronic Components Datasheet

MC88916 Datasheet

LOW SKEW CMOS PLL CLOCK DRIVER WITH PROCESSOR RESET

No Preview Available !

MC88916 pdf
MC88916
Q3 1
VCC 2
MR 3
RST_IN 4
VCC(AN) 5
RC1 6
GND(AN) 7
SYNC 8
GND 9
Q0 10
20 GND
19 2X_Q
18 Q/2
17 VCC
16 Q2
15 GND
14 RST_OUT(LOCK)
13 PLL_EN
12 Q1
11 VCC
Pinout: 20–Lead Wide SOIC Package (Top View)
Description of the RST_IN/RST_OUT(LOCK) Functionality (continued)
After the system start–up is complete and the 88916 is
phase–locked to the SYNC input signal (RST_OUT high), the
processor reset functionality can be utilized. When the
RST_IN pin is toggled low (min. pulse width=10nS),
RST_OUT(LOCK) will go to the low state and remain there
for 1024 cycles of the ‘Q’ output frequency (512 SYNC
cycles). During the time in which the RST_OUT(LOCK) is
actively pulled low, all the 88916 clock outputs will continue
operating correctly and in a locked condition to the SYNC
input (clock signals to the 68030/040 family of processors
must continue while the processor is in reset). A propagation
delay after the 1024th cycle RST_OUT(LOCK) goes back to
the high impedance state to be pulled high by the resistor.
Power Supply Ramp Rate Restriction for Correct 68030
Processor Reset Operation During System Start–up
Because the RST_OUT(LOCK) pin is an indicator of
phase–lock to the reference source, some constraints must
be placed on the power supply ramp rate to make sure the
RST_OUT(LOCK) signal holds the processor in reset during
system start–up (power–up). With the recommended loop
filter values (see Figure 7) the lock time is approximately
10ms. The phase–lock loop will begin attempting to lock to a
reference source (if it is present) when VCC reaches 2V. If
the VCC ramp rate is significantly slower than 10ms, then the
PLL could lock to the reference source, causing
RST_OUT(LOCK) to go high before the 88916 and 68030
processor is fully powered up, violating the processor reset
specification. Therefore, if it is necessary for the RST_IN pin
to be held high during power–up, the VCC ramp rate must be
less than 10mS for proper 68030/040 reset operation.
This ramp rate restriction can be ignored if the RST_IN pin
can be held low during system start–up (which holds
RST_OUT low). The RST_OUT(LOCK) pin will then be
pulled back high 1024 cycles after the RST_IN pin goes high.
CAPACITANCE AND POWER SPECIFICATIONS
Symbol
Parameter
CIN
CPD
PD1
Input Capacitance
Power Dissipation Capacitance
Power Dissipation at 33MHz With 50
Thevenin Termination
PD2 Power Dissipation at 33MHz With 50
Parallel Termination to GND
Value Typ
4.5
40
15mW/Output
90mW/Device
37.5mW/Output
225mW/Device
Unit
pF
pF
mW
mW
Test Conditions
VCC = 5.0V
VCC = 5.0V
VCC = 5.0V
T = 25°C
VCC = 5.0V
T = 25°C
MOTOROLA
2 TIMING SOLUTIONS
BR1333 — REV 5


Part Number MC88916
Description LOW SKEW CMOS PLL CLOCK DRIVER WITH PROCESSOR RESET
Maker Motorola
Total Page 9 Pages
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