SEMICONDUCTOR TECHNICAL DATA
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Low Skew CMOS PLL Clock Driver
With Power-Down/Power-Up Feature
The MC88920 Clock Driver utilizes phase–locked loop technology to
lock its low skew outputs’ frequency and phase onto an input reference
clock. It is designed to provide clock distribution for CISC microprocessor
or single processor RISC systems. The RST_IN/RST_OUT(LOCK) pins
provide a processor reset function designed specifically for the
MC68/EC/LC030/040 microprocessor family.
The PLL allows the the high current, low skew outputs to lock onto a
single clock input and distribute it with essentially zero delay to multiple
locations on a board. The PLL also allows the MC88920 to multiply a low
frequency input clock and distribute it locally at a higher (2X) system
LOW SKEW CMOS PLL
• 2X_Q Output Meets All Requirements of the 20 and 25MHz 68040
Microprocessor PCLK Input Specifications
• Three Outputs (Q0–Q2) With Output–Output Skew <500ps and Six
Outputs Total (Q0–Q2, Q3, 2X_Q,) With <1ns Skew Each Being Phase
and Frequency Locked to the SYNC Input
• The Phase Variation From Part–to–Part Between SYNC and the ‘Q’
Outputs Is Less Than 600ps (Derived From the TPD Specification,
Which Defines the Part–to–Part Skew)
• SYNC Input Frequency Range From 5MHZ to 2X_Q FMax/4
PLASTIC SOIC PACKAGE
• Additional Outputs Available at 2X and ÷2 the System ‘Q’ Frequency.
Also a Q (180° Phase Shift) Output Available.
• All Outputs Have ±36mA Drive (Equal High and Low) CMOS Levels. Can Drive Either CMOS or TTL Inputs. All Inputs Are
• Test Mode Pin (PLL_EN) Provided for Low Frequency Testing
• Special Power–Down Mode With 2X_Q, Q0, and Q1 Being Reset (With MR), and Other Outputs Remain Running. 2X_Q, Q0
and Q1 Are Guaranteed to Be in Lock 3 Clock Cycles After MR Is Negated
Three ‘Q’ outputs (Q0–Q2) are provided with less than 500ps skew between their rising edges. The Q3 output is inverted (180°
phase shift) from the ‘Q’ outputs. A 2X_Q output runs at twice the ‘Q’ output frequency. The 2X_Q output is ideal for 68040
systems which require a 2X processor clock input, and it meets the tight duty cycle spec of the 20 and 25MHz 68040. The Q/2
output runs at 1/2 the ‘Q’ frequency. This output is fed back internally, providing a fixed 2X multiplication from the ‘Q’ outputs to
the SYNC input. Since the feedback is done internally (no external feedback pin is provided) the input/output frequency
relationships are fixed.
In normal phase–locked operation the PLL_EN pin is held high. Pulling the PLL_EN pin low disables the VCO and puts the
88920 in a static ‘test mode’. In this mode there is no frequency limitation on the input clock, which is necessary for a low
frequency board test environment.
The RST_OUT(LOCK) pin doubles as a phase–lock indicator. When the RST_IN pin is held high, the open drain RST_OUT
pin will be pulled actively low until phase–lock is achieved. When phase–lock occurs, the RST_OUT(LOCK) is released and a
pull–up resistor will pull the signal high. To give a processor reset signal, the RST_IN pin is toggled low, and the
RST_OUT(LOCK) pin will stay low for 1024 cycles of the ‘Q’ output frequency after the RST_IN pin is brought back high.
Description of the RST_IN/RST_OUT(LOCK) Functionality
The RST_IN and RST_OUT(LOCK) pins provide a 68030/040 processor reset function, with the RST_OUT pin also acting as
a lock indicator. If the RST_IN pin is held high during system power–up, the RST_OUT pin will be in the low state until steady
state phase/frequency lock to the input reference is achieved. 1024 ‘Q’ output cycles after phase–lock is achieved the
RST_OUT(LOCK) pin will go into a high impedance state, allowing it to be pulled high by an external pull–up resistor (see the
AC/DC specs for the characteristics of the RST_OUT(LOCK) pin). If the RST_IN pin is held low during power–up, the
RST_OUT(LOCK) pin will remain low.
© Motorola, Inc. 1995