MCM69D618 Datasheet | Motorola Semiconductor

features mon data input and data output buffers and incorporates input and output registers on- board with high speed SRAM. The MCM69D618 allows the user to concurrently perform reads, writes, or pass- through cycles in bination on the two data ports. The two address ports (AX, AY) determine the read or write locations for their respective data ports (DQX, DQY). The synchronous design allows for precise cycle control with the use of an external single clock (K). All signal pins except output enables (GX, GY) are registered on the rising edge of clock (K). The pass- through feature allows data to be passed from one port to the other, in either direction. The PTX input must be asserted to pass data from port X to port Y. The PTY will likewise pass data from port Y to port X. A pass- through operation takes precedence over a read operation. For the case when AX and AY are the same, certain protocols are followed. If both ports are read, the reads occur normally. If one port is written and the other is read, the read from the array will occur before the data is written. If both ports are written, only the data on DQY will be written to the array. - - - - - - - - - - - - - - Single 3.3 V ± 5% Power Supply Fast Access Times: 6/8 ns Max Throughput of 1.49 Gigabits/Second Single Clock Operation Address, Data Input, E1, E2, PTX, PTY, WX, WY, and Data Output Registers On- Chip 83 MHz Maximum Clock Frequency Self Timed Write Two Bi- Directional Data Buses Can be Configured as Separate I/O Pass- Through Feature Asynchronous Output Enables (GX, GY) LVTTL patible I/O Concurrent Reads and Writes 100- Pin TQFP Package - Routers - Shared Memory TQ PACKAGE 100 LEAD TQFP CASE 983A- 01 Suggested Applications - ATM - Ethernet Switches - Cell/Frame Buffers - SNA Switches Product Family Configurations Part Number MCM69D536 MCM69D618 MCM67Q709A MCM67Q909 Dual Address n n Single Address Note 1 Note 1 Dual I/O n n n n Separate I/O Note 2 Note 2 Configuration 32K x 36 64K x 18...