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MCM69D618 - 64K x 18 Bit Synchronous Dual I/O / Dual Address SRAM

General Description

Pin Locations 40, 38, 36, 34, 32, 30, 100, 98, 85, 83, 42, 44, 46, 48, 50, 81 39, 37, 35, 33, 31, 29, 99, 97, 84, 82, 43, 45, 47, 49, 51, 80 52, 56, 58, 62, 64, 69, 71, 75, 77, 3, 5, 9, 11, 16, 18, 22, 24, 28 53, 57, 59, 63, 65, 68, 70, 74, 76, 4, 6, 10, 12, 15, 17, 21, 23, 27 90 91 92 Symbol AX0

Key Features

  • common data input and data output buffers and incorporates input and output registers on.
  • board with high speed SRAM. The MCM69D618 allows the user to concurrently perform reads, writes, or pass.
  • through cycles in combination on the two data ports. The two address ports (AX, AY) determine the read or write locations for their respective data ports (DQX, DQY). The synchronous design allows for precise cycle control with the use of an external single clock (K). All signal pins except.

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Full PDF Text Transcription (Reference)

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM69D618/D 64K x 18 Bit Synchronous Dual I/O, Dual Address SRAM The MCM69D618 is a 1M–bit static random access memory, organized as 64K words of 18 bits. It features common data input and data output buffers and incorporates input and output registers on–board with high speed SRAM. The MCM69D618 allows the user to concurrently perform reads, writes, or pass–through cycles in combination on the two data ports. The two address ports (AX, AY) determine the read or write locations for their respective data ports (DQX, DQY). The synchronous design allows for precise cycle control with the use of an external single clock (K). All signal pins except output enables (GX, GY) are registered on the rising edge of clock (K).