MCM69Q536 Description
MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM69Q536/D Advance Information MCM69Q536 32K x 36 Bit Synchronous Separate I/O SRAM The Motorola MCM69Q536 is a 1 Megabit static random access memory, organized as 32K words of 36 bits.
MCM69Q536 Key Features
- a data input (D) and a data output (Q) port. The synchronous design allows for precise cycle control with the use of an
- D35), data output (Q0
- Q35), write enable (W), chip enables (E1, E2), and pass-through enable (PT) are registered on the rising edge of clock (
- Routers
- Shared Memory