Overview: SSSS7777LLLL6666444413318668UUUU2222MMMM Preliminary
22MMxx3366 && 44MMxx1188 DDDDRRIIII++ CCIIOO BBLL22 SSRRAAMM ww// OODDTT 72Mb DDRII+ CIO BL2 w/ ODT SRAM Specification
(2.5 Clock Read Latency)
165FBGA with Pb & Pb Free
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Rev. 0.0 Oct. 2012 -1- S7L6436U2M S7L6418U2M Preliminary
2Mx36 & 4Mx18 DDRII+ CIO BL2 SRAM w/ ODT Document Title
2Mx36 & 1Mx18 - Bit DDRII+ CIO Burst Length of 2 SRAM w/ ODT (2.5 Clock Read Latency) Revision History Rev. No. History 0.0 Initial Draft Draft Date
Oct. 2012 Remark
Preliminary Rev. 0.0 Oct. 2012 -2- S7L6436U2M S7L6418U2M Preliminary
2Mx36 & 4Mx18 DDRII+ CIO BL2 SRAM w/ ODT 2Mx36 & 1Mx18 - Bit DDRII+ CIO Burst Length of 2 SRAM w/ ODT (2.
