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NXP Semiconductors Electronic Components Datasheet

74ABT861 Datasheet

10-bit bus transceiver

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Philips Semiconductors
8-bit transceiver with 9-bit parity checker/
generator and flag latch (3-State)
Product specification
74ABT853
FEATURES
Low static and dynamic power dissipation with high speed and
high output drive
Open-collector ERROR output
Output capability: +64mA/–32mA
Latch-up protection exceeds 500mA per Jedec Std 17
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
Power-up 3-State
Live insertion/extraction permitted
DESCRIPTION
The 74ABT853 high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
The 74ABT853 is an octal transceiver with a parity
generator/checker and is intended for bus–oriented applications.
When Output Enable A (OEA) is High, it will place the A outputs in a
high impedance state. Output Enable B (OEB) controls the B
outputs in the same way.
The parity generator creates an odd parity output (PARITY) when
OEB is Low. When OEA is Low, the parity of the B port, including
the PARITY input, is checked for odd parity. When an error is
detected, the error data is sent to the input of a latch. The error data
can then be passed, stored, cleared, or sampled depending on the
ENABLE and CLEAR control signals.
If both OEA and OEB are Low, data will flow from the A bus to the B
bus and the part is forced into an error condition which creates an
inverted PARITY output. This error condition can be used by the
designer for system diagnostics.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
tPLH
tPHL
tPLH
tPHL
CIN
CI/O
ICCZ
Propagation delay
An to Bn or Bn to An
Propagation delay
An to PARITY
Input capacitance
I/O capacitance
Total supply current
CONDITIONS
Tamb = 25°C; GND = 0V
CL = 50pF; VCC = 5V
CL = 50pF; VCC = 5V
VI = 0V or VCC
Outputs disabled; VO = 0V or VCC
Outputs disabled; VCC =5.5V
TYPICAL
3.4
7.4
4
7
50
UNIT
ns
ns
pF
pF
µA
ORDERING INFORMATION
PACKAGES
24-Pin Plastic DIP
24-Pin plastic SO
24-Pin Plastic SSOP Type II
24-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74ABT853 N
74ABT853 D
74ABT853 DB
74ABT853 PW
NORTH AMERICA
74ABT853 N
74ABT853 D
74ABT853 DB
74ABT853PW DH
DWG NUMBER
SOT222-1
SOT137-1
SOT340-1
SOT355-1
PIN CONFIGURATION
LOGIC SYMBOL
OEA 1
A0 2
A1 3
A2 4
A3 5
A4 6
A5 7
A6 8
A7 9
ERROR 10
CLEAR 11
GND 12
24 VCC
23 B0
22 B1
21 B2
20 B3
19 B4
18 B5
17 B6
16 B7
15 PARITY
14 OEB
13 ENABLE
TOP VIEW
1995 Sep 06
SA00262
1
23456789
A0 A1 A2 A3 A4 A5 A6 A7
14 OEB
1 OEA
PARITY
15
11 CLEAR
ERROR
10
13 ENABLE
B0 B1 B2 B3 B4 B5 B6 B7
23 22 21 20 19 18 17 16
SA00263
853-1672 15702


NXP Semiconductors Electronic Components Datasheet

74ABT861 Datasheet

10-bit bus transceiver

No Preview Available !

Philips Semiconductors
8-bit transceiver with 9-bit parity checker/
generator and flag latch (3-State)
Product specification
74ABT853
PIN DESCRIPTION
SYMBOL
A0 – A7
B0 – B7
OEA
OEB
PARITY
ERROR
CLEAR
ENABLE
GND
VCC
PIN NUMBER
2, 3, 4, 5, 6, 7, 8, 9
23, 22, 21, 20, 19, 18, 17, 16
1
14
15
10
11
13
12
24
NAME AND FUNCTION
A port 3–State inputs/outputs
B port 3–State inputs/outputs
Enables the A outputs when Low
Enables the B outputs when Low
Parity output/input
Error output (open collector)
Clears the error flag register when Low
Enable input (active-Low)
Ground (0V)
Positive supply voltage
FUNCTION TABLE
INPUTS
OUTPUTS
MODE
OEB OEA
An
Σ OF HIGHS
Bn + PARITY
Σ OF HIGHS
An
Bn PARITY
A data to B bus and generate odd parity output
B data to A bus and check for parity error1
A bus and B bus disabled2
LH
HL
HH
Odd
Even
(output)
X
(output)
X
X
(input) An
Bn (input)
ZZ
L
H
(input)
Z
A data to B bus and generate inverted parity output
LL
Odd
Even
(output)
(input) An
H
L
NOTES:
1. Error checking is detailed in the Error Flag Function Table below.
2. When ENABLE is Low, ERROR is Low if the sum of A inputs is even or ERROR is High if the sum of A inputs is odd.
ERROR FLAG FUNCTION TABLE
INPUTS
MODE
ENABLE
CLEAR
Pass
LL
Sample
Clear
LH
HL
Bn + PARITY
Σ OF HIGHS
Odd
Even
Odd
Even
X
X
Store
HH
X
H = High voltage level steady state
L = Low voltage level steady state
X = Don’t care
Z = High impedance ”off” state
INTERNAL NODE
POINT ”P”
H
L
H
L
X
X
X
OUTPUT
PRE–STATE
ERRORn–1
X
H
X
L
X
L
H
ERROR
OUTPUT
H
L
H
L
L
H
L
H
1995 Sep 06
2


Part Number 74ABT861
Description 10-bit bus transceiver
Maker NXP
Total Page 7 Pages
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