74LVC32244A Datasheet | NXP Semiconductors

FEATURES - 5 V tolerant inputs/outputs for interfacing with 5 V logic - Wide supply voltage range of 1.2 to 3.6 V - CMOS low power consumption - MULTIBYTE™ flow-trough standard pin-out architecture - Low inductance multiple power and ground pins for minimum noise and ground bounce - Direct interface with TTL levels - Bus hold on data inputs (74LVCH32244A only) - Typical output ground bounce voltage: VOLP <0.8 V at VCC = 3.3 V; Tamb = 25 °C - Typical output VOH undershoot voltage: VOHV >2 V at VCC = 3.3 V; Tamb = 25 °C - Power-off disabled outputs, permitting live insertion - Plastic fine-pitch ball grid array package. DESCRIPTION 74LVC32244A; 74LVCH32244A The 74LVC(H)32244A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS patible TTL families. Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation, outputs can handle 5 V. These features allow the use of these devices in a mixed 3.3 and 5 V environment. The 74LVC(H)32244A is a 32-bit non-inverting buffer/line driver with 3-state outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH on input n OE causes the outputs to assume a high-impedance OFF-state. To ensure the high-impedance state during power-up or power-down, input n OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The 74LVCH32244A bus hold data input circuit eliminates the need for external pull-up resistors to hold unused or floating data inputs at a valid logic level (see Fig.3). QUICK REFERENCE DATA Ground = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns. SYMBOL t PHL/t PLH CI CPD Note 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in p F; VCC = supply voltage in Volts; Σ(CL × VCC2 × fo) = sum of the...