* 5 V tolerant inputs/outputs, for interfacing with 5 V logic
* Supply voltage range from 1.2 V to 3.6 V
* CMOS low power consumption
* Direct interface with TTL levels
* High-impedance when VCC = 0 V
* Flow-through pinout architecture
* Complies with JEDEC standard:
74LVC573A Datasheet (153.31 KB)
74LVC573A
153.31 KB
Octal d-type transparent latch.
74LVC573A Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state Rev. 5 19 February 2013 Product data sheet 1. General.
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