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74LVC573A-Q100 - Octal D-type transparent latch

Description

The 74LVC573A-Q100 consists of eight D-type transparent latches, featuring separate D-type inputs for each latch and 3-state true outputs for bus-oriented applications.

A Latch Enable (LE) input and an Output Enable (OE) input are common to all internal latches.

Features

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1).
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C.
  • 5 V tolerant inputs/outputs, for interfacing with 5 V logic.
  • Supply voltage range from 1.2 V to 3.6 V.
  • CMOS low power consumption.
  • Direct interface with TTL levels.
  • High-impedance when VCC = 0 V.
  • Flow-through pinout architecture.
  • Complies with JEDEC standard:.
  • JESD8-7A (1.65 V.

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Full PDF Text Transcription

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74LVC573A-Q100 Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state Rev. 3 — 30 March 2020 Product data sheet 1. General description The 74LVC573A-Q100 consists of eight D-type transparent latches, featuring separate D-type inputs for each latch and 3-state true outputs for bus-oriented applications. A Latch Enable (LE) input and an Output Enable (OE) input are common to all internal latches. When LE is HIGH, data at the Dn inputs enters the latches. In this condition, the latches are transparent, that is, a latch output changes each time its corresponding D-input changes. When LE is LOW, the latches store the information that was present at the D-inputs one set-up time preceding the HIGH-to-LOW transition of LE.
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